3.3" LCD display and SYNCS !

[shawnxyh]

Hi guys, I just started my own Uzebox project and is trying to implement it using a LCD display instead of TV.

However, the LCD comes with D51E5TA7601, a Driver IC for 260K-color display on HVGA a-Si TFT and this brings to the question

There are 3 interface provided by the driver IC:
SERIAL PERIPHERAL INTERFACE
VSYNC INTERFACE
RGB INTERFACE

And we would like to use the RGB interface but the control signal for RGB interface are HSYNC and VSYNC.
However, the signal that comes out from atmel644 is Composite sync ( PB0 ) so is there any way to convert this signal into HSYNC and VSYNC?
Or is there any simpler ways to realize it using other interfaces provided by the driver ?

Datasheet for the Driver IC : http://www.displaytech-us.com/pdf/appli ... TA7601.pdf
Datasheet for the LCD display: http://www.displaytech-us.com/pdf/FullS ... FT-V20.pdf

Any idea / help is greatly appreciated !!!

[uze6666]

I guess Hsync and vsync could be separated, but the kernel would need to be altered I'm afraid and all games recompiled. I see that the controller also needs an additional pixel clock. That would require another timer output and more modifications to the kernel. But it's all possible for a custom Uzebox. Someone already hacked the kernel to support a similar screen a while ago.

-Uze

[shawnxyh]

Thanks a lot forthe comment!

I think I am going to use a separator IC to get Hsync and Vsync signals.
Regarding DOT CLK, think I am using a frequency divider to provide a 6MHz to clock the pixels.

However, there is one more control signal besides Vsync,Hsync,and DOT CLK, the ENABLE signal.
this signal cant be pulled low always to keep enabling it seems, otherwise extra pixels are displayed when not needed and everything screws up, I guess.

Do you have any idea how to write this signal in the kernel or I can somehow provide it from the hardware ?

Thanks again !

[uze6666]

It depends what the ENABLE signal is supposed to do. Is it some signal that has to be inactive during HBLANK/VBLANK? If so that should not be too hard to add in the kernel.

-Uze

[shawnxyh]

Yeah I think you are right

Details of ENABLE can be found page 61 of
http://www.displaytech-us.com/pdf/appli ... TA7601.pdf

It is active-low signal which is 1(inactive) during VBLANK and during HBLANK.
The rest of the time is 0 (active).

But it's also has more to do with DOT CLK to be exactly precise in timing sequence but this is the general idea.

If ENABLE can be realized I think its very likely that the LCD can be driven under RGB interface.

During the active time the pixel are written into DDRAM and is read from it and displayed onto LCD when inactive, I suppose.




Thanks again for the help!!!